How Will You Manage Power, Performance, and Reliability in the Chiplet Era?

Chiplet-based architectures, 2.5D integration, and system-in-package (SiP) designs are unlocking new levels of performance, scalability, and design flexibility. But moving beyond the monolithic SoC also introduces complex interactions among dies, interconnects, substrates, and packaging, creating new challenges in power delivery, thermal management, mechanical integrity, test, and long-term reliability.

At the same time, manufacturers must manage compound yield and rising production costs as the industry progresses from Known-Good-Die (KGD) to increasingly complex multi-die assemblies and Known-Good-Stack (KGS) methodologies. Traditional test and monitoring approaches are no longer enough to provide the visibility needed across die boundaries and throughout the product lifecycle.

Join our industry experts for a 40-minute webinar discussion exploring how design, test, manufacturing, and system teams are addressing these challenges through shift-left methodologies, evolving test standards, and deeper lifecycle observability and how the semiconductor ecosystem is working to deliver robust, power-efficient, and reliable multi-die systems at scale. 

What you will learn:
  • How emerging standards are enabling more effective test access across complex multi-die systems
  • Why shift-left observability is essential for identifying power, thermal, and reliability risks earlier
  • How production test strategies are evolving to address compound yield, KGD, and KGS requirements
  • How package-level power delivery and thermal interactions can affect system performance and operating margins
  • How lifecycle monitoring can improve in-field reliability, optimize performance, and help extend system lifetime

Wednesday, August 26, 2026 | 10 AM PT / 1 PM ET / 7 PM ET

All registrants will receive the recording after the live event.

Speaker Bios

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Nir Sever
Senior Director, Business Development
proteanTecs

Nir Sever brings with him more than 30 years of technological and managerial experience in advanced VLSI engineering. Prior to joining ProteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high speed networking Semiconductors. Before that, he served for 9 years as Senior Director of VLSI Design and Technologies for Zoran Corporation, a recognized world leader in Semiconductors for the highly competitive Consumer Electronics Market. Nir was responsible for driving Zoran silicon technologies and delivering more than 10 new silicon products each year. Prior to Zoran, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions and Zoran Microelectronics. Nir earned his BSEE degree from the Technion - Israel Institute of Technology.

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Vineet Pancholi
Senior Director, Manufacturing & Test,
Amkor Technology

Vineet joined Amkor in January 2019 as the Manufacturing Test Technologist. He leads test technology development and deployment for 2.5D/3D Advanced Packages, high-speed digital production test methodologies and 5G RF. Before joining Amkor, Vineet worked at Microchip Technology for 6 years and Intel Corporation for 19 years. At Microchip, he was the lead test content developer for 8 and 16bit microcontrollers with a variety of Analog and Mixed Signal peripherals. At Intel, he held a variety of test roles, including tester supplier management, test technology development for burn-in, final and system level test. He owned the Burn In Platform’s Electrical sub-system and architected the RF tester architecture for the organically developed Test Platform. Vineet holds a patent on semiconductor device testers and has earned master’s degrees in physics and electrical engineering from Arizona State University.

Register for the webinar

All registrants will receive the recording after the live event.

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